PLR v1.1

PLR is an automatic parallelizer and CUDA code generator for linear recurrences, including prefix sums and 1D digital IIR filters, as described in this ASPLOS paper.

To generate PLR code for a specific recurrence, enter the signature of the recurrence in the text box below and click the submit button. Note that the (generated) PLR code is protected by the license included in the beginning of the code.

For example, to generate scalar, first-order, integer prefix-sum code, enter the signature "1 : 1" without any quotes or parentheses (note the spaces before and after the colon). Table 1 and the surrounding text in the ASPLOS paper explain how to create the signatures for other recurrences.


Assuming the generated code has been stored in a file called, it can be compiled as follow:

nvcc -O3 -arch=sm_35 -o plr

To execute the included test code and have it compute a recurrence over 100,000,000 elements, enter:

./plr 100000000

The PLR code has been tested on Pascal-, Maxwell-, Kepler-, Volta-, and Turing-based GPUs with integer and floating-point recurrences. It requires at least compute capability 3.0. If an unstable recurrence is entered, the code may not compile because of correction factors that are ±∞ or NaNs.


S. Maleki and M. Burtscher. "Automatic Hierarchical Parallelization of Linear Recurrences." 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems. March 2018. [pdf] [pptx] [video]

This work has been supported in part by the National Science Foundation under Grant No. 1406304 as well as by equipment donations from Nvidia Corporation.

Official Texas State University Disclaimer